AN-1109APPLICATION NOTEOne Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.comRecommendations for Control of Radiated Emissions with iCoupler Devicesby Brian Kennedy and Mark CantrellINTRODUCTIONiCoupler data isolation products can readily meet CISPR 22Class A (and FCC Class A) emissions standards, as well as themore stringent CISPR 22 Class B (and FCC Class B) standards inan unshielded environment, with proper PCB design choices.This application note examines PCB-related EMI mitigationtechniques, including board layout and stack-up issues.Several standards for radiated emissions exist. In the U.S., theFederal Communications Commission (FCC) controls thestandards and test methods. In Europe, the InternationalElectrotechnical Commission (IEC) generates standards, andCISPR test methods are used for evaluating emissions. Themethods and pass/fail limits are slightly different under the twostandards. Although this application note references IEC standards, all results are applicable to both standards.Data transitions at the input of iCoupler digital isolators areencoded as narrow pulses that are used to send informationacross the isolation barrier. These 1 ns pulses have peakcurrents of up to 70 mA and may cause radiated emissions andconducted noise if not considered during printed circuit board(PCB) layout and construction. This application note identifiesthe radiation mechanisms and offers specific guidance onaddressing them through high frequency PCB designtechniques.Control of emissions from signal cables and chassis shieldingtechniques are outside of the scope of this application note.EMI MITIGATION OVERVIEWBest-practice techniques for EMI mitigation include acombination of the use of input-to-output ground planestitching capacitance, edge guarding, and the reduction ofsupply voltage levels for noise reduction. For the purposesof this application note, a 4-layer board was designed andmanufactured using materials and structures well withinindustry practice.The EMI reduction examples used in this application note arebased on the 4-channel iCoupler products, but the informationis relevant to all the iCoupler product families, examples of whichare shown in Figure 1.For information on reducing emissions from products usingisoPower, integrated isolated power, refer to the AN-0971Application Note, which includes additional recommendationsand techniques.ADuM14xx, ADuM24xx,ADuM34xx, ADuM44xx,ADuM744xADuM13xx, ADuM33xxADuM12xx, ADuM22xx,ADuM32xx09713-001ADuM1100, ADuM3100Figure 1. Example of iCoupler Device FamiliesRev. 0 Page 1 of 20

AN-1109Application NoteTABLE OF CONTENTSIntroduction . 13.3 V Operation .9EMI Mitigation Overview . 1Recommended Design Practices. 10Revision History . 2Meeting Isolation Standards . 10Sources of Radiated Emissions . 3Example Board. 10Edge Emissions . 3Gap Board Layout Results. 12Input-to-Output Dipole Emissions. 3Conclusions . 14Sources of Conducted Noise . 5Appendix A—PCB Examples. 15EMI Mitigation Techniques . 6Low Noise PCB Example. 15Input-to-Output Stitching . 6Gap PCB Example. 17Edge Guarding . 8References. 19Interplane Capacitance . 8REVISION HISTORY4/11—Revision 0: Initial VersionRev. 0 Page 2 of 20

Application NoteAN-1109SOURCES OF RADIATED EMISSIONSThere are two potential sources of emissions in PCBs: edgeemissions and input-to-output dipole emissions.INPUT-TO-OUTPUT DIPOLE EMISSIONS Ground and power noise, generated by inadequate bypassof high power current sinks. Cylindrically radiated magnetic fields coming frominductive via penetrations radiated out between boardlayers eventually meeting the board edge. Stripline image charge currents spreading from highfrequency signal lines routed too close to the edge ofthe board.1Edge emissions are generated where differential noise frommany sources meet the edge of the board and leak out of aplane-to-plane space, acting as a wave guide (see Figure 2).09713-0028GROUNDPOWER16Edge emissions occur when unintended currents meet the edgesof ground and power planes. These unintended currents canoriginate fromThe primary mechanism for radiation is an input-to-outputdipole generated by driving a current source across a gapbetween ground planes. Isolators, by their very nature, drivecurrent across gaps in ground planes. The inability of highfrequency image charges associated with the transmitted current to return across the boundary causes differential signalsacross the gap driving the dipole. In some cases, this may be alarge dipole, as shown in Figure 4. A similar mechanism causeshigh frequency signal lines to radiate when crossing splits in theground and power planes. This type of radiation is predominantly perpendicular to the ground planes.9EDGE EMISSIONS09713-004Figure 2. Edge Radiation from an Edge Matched Ground Power PairGROUNDFigure 4. Dipole Radiation Between Input and OutputhSIGNALThe ADuM140x devices serve as a good example of the issuesinvolved in generating and mitigating emissions.09713-00320hPOWERFigure 3. Edge Radiation from an Edge Mismatched Power Ground PairAt the edge boundary, there are two limiting conditions: theedges of the ground and power planes are aligned as in Figure 2or one edge is pulled back by some amount as shown in Figure 3.In the first case, with aligned edges, there is some reflectionback into the PCB and some transmission of the fields out ofthe PCB. In the second case, the edges of the board make astructure similar to the edge of a patch antenna. When theedges mismatch by 20h where h is the plane-to-plane pacing,the fields efficiently couple out of the PCB, resulting in highemissions (see “Minimizing EMI Caused by Radially PropagatingWaves Inside High Speed Digital Logic PCBs” in the Referencessection). These two limiting cases are important considerationsas described in the edge treatment of the PCB in the EdgeGuarding section.When operating under a full 5 V VDD supply voltage, the peakcurrents of the transmitter pulses is about 70 mA, and thesepulses are 1 ns wide with fast edge rates.Bypass capacitors are intended to provide this high frequencycurrent locally. The capacitor must provide large charge reserves.At the same time, the capacitor should have a very low seriesresistance at high frequencies in the 100 MHz to 1 GHz range.Even with multiple low ESR capacitors near the pins, inductively limited bypassing generates voltage transients, and thenoise may be injected onto the ground and power planes. Theself-resonant frequency of capacitors should be considered.Having multiple capacitors of various sizes, 100 nF, 10 nF, and1 nF, may help reduce this effect.Figure 5 shows emissions data collected in an anechoic chambertaken with a 4-channel ADuM1402 with 5 V supplies, runningat 1 Mbps signal frequency and using a standard 4-layer PCB,but without an input-to-output ground plane stitchingcapacitance.Rev. 0 Page 3 of 20

AN-1109Application NoteCHAMBER EN55022, CLASS B, RADIATED EMISSIONS PRESCANACTV DET: PEAKREF LEVELMEAS DET: PEAK60.0dBµVMKR 873.3MHz38.56dBµVCHAMBER EN55022, CLASS B, RADIATED EMISSIONS PRESCANREF LEVELACTV DET: PEAK50.0dBµVMEAS DET: PEAKMKR 682.7MHz23.38dBµVPREAMP ONREF 60.0dBµVREF 50.0dBµVLOG5dB/#ATN0dBLOG5dB/#ATN0dB40dBµVPREAMP ON47dBµVCISPR 22 CLASS A47dBµV37dBµVCISPR 22 CLASS ACISPR 22 CLASS B40dBµV30dBµV37dBµVCISPR 22 CLASS B30dBµVSTOPAVG BW 300kHz1.0000GHzSWP 909msFigure 5. Anechoic Chamber Emissions from a Standard 4-Layer Board with4-Channel ADuM1402 at 1 MbpsVA SBSC FCACORRSTART 30.0MHzL#1F BW 120kHzSTOPAVG BW 300kHz1.0000GHzSWP 909ms09713-006START 30.0MHzL#1F BW 120kHz09713-005VA SBSC FCACORRFigure 6. Anechoic Chamber Emissions from a Low Noise 4-Layer Board with300 pF Stitching Capacitance and 4-Channel ADuM1402 at 1 MbpsThe emissions data for this board, as shown in Figure 5, passesCISPR 22 Class A emissions standards by approximately 6 dBμVin the 30 MHz to 230 MHz range (40 dBμV requirement). Incontrast, Figure 6 shows the results of a low noise, 4-layer boardusing a 300 pF stitching capacitance. This was tested under thesame conditions as the standard board but passes CISPR 22Class A and CISPR 22 Class B by a wide margin. The EMIMitigation Techniques section describes how to use some recommended PC layout techniques like those used on the low noiseboard to control radiated emissions.Rev. 0 Page 4 of 20

Application NoteAN-1109SOURCES OF CONDUCTED NOISELarge currents and frequencies also generate conducted noiseon the ground and power planes. This can be addressed withthe same techniques for radiated emissions because the causesand remedies for both types of EMI can be improved with thesame PCB ground and power structures.The inability of the bypass capacitors and ground/power planesto provide adequate high frequency current to the iCouplerdevice causes VDD noise. The iCoupler isolator transmits dataacross the transformer in bursts of 1 ns pulses with an ampli-tude of 70 mA. An ideal bypass capacitor of 100 nF should beadequate to supply the ac component of the current. However,bypass capacitors are not ideal and may connect to the groundor power planes through an inductive via. In addition, a largedistance between ground and power planes creates a largeinductance between them, which restricts the ability to supplycurrent quickly. These factors may contribute to a large fractionof a volt of high frequency noise on the VDD plane.Rev. 0 Page 5 of 20

AN-1109Application NoteEMI MITIGATION TECHNIQUESMany mitigation techniques are available to the designer. Severaltechniques that apply directly to the iCoupler devices are identified in this section. There are trade-offs between how aggressivelyto address EMI to pass IEC or FCC emissions levels and therequirements of the design, including cost and performance.There are at least three options to form a stitching capacitance.To take full advantage of PCB related EMI mitigation practices,a PCB should rely on having relatively continuous ground andpower planes with the ability to specify relative positions anddistances in the stack-up. This suggests the use of at least threelayers to take full advantage of these techniques: ground, power,and signal planes. For practical considerations in board manufacture, a 4-layerboard is the minimum stack-up. More layers are acceptableand can be used to greatly enhance the effectiveness of therecommendations. If a 2-layer board is used, a safety stitchingcapacitor can be used to reduce emissions, as described in theInput-to-Output Stitching section.The following techniques are effective in reducing EMIradiation and on-board noise: Input-to-output ground plane stitchingEdge guardingInterplane capacitive bypassPower control (3.3 V operation)Circuit boards with test structures were prepared to evaluateeach of these EMI mitigation techniques using the ADuM140x.The layout of each board was varied as little as possible to allowmeaningful comparison of results. Testing was conducted at anEMI test facility under standard conditions for CISPR 22 Class Bcertification. Results are shown in Figure 14 to Figure 17 andsummarized in Table 4 to Table 7.INPUT-TO-OUTPUT STITCHINGWhen current flows along PCB traces, an image charge followsalong the ground plane beneath the trace. If the trace crosses agap in the ground plane, the image charge cannot follow along.This creates differential currents and voltages in the PCB, leadingto radiated and conducted emissions. The solution is to providea path for the image charge to follow the signal. Standard practice is to place a stitching capacitor in proximity to the signalacross the split in the ground plane (see “PCB Design for RealWorld EMI Control” in the References section). This sametechnique works to minimize radiation between ground planesdue to the operation of iCoupler isolators. A safety rated capacitor applied across the barrier.Ground and power planes on an interior layer can beextended into the isolation gap of the PCB to form anoverlapping stitching capacitor.A floating metal plane can span the gap between theisolated and nonisolated sides on an interior layer, asshown in Figure 8.Each option has advantages and disadvantages in effectivenessand area required to implement. Note that, for medical applications, the total isolation capacitance allowed between isolatedground and earth ground may only be as large as 10 pF to 20 pF.Safety Stitching CapacitorStitching capacitance can be implemented with a simple ceramiccapacitor across the isolation barrier. Capacitors with guaranteed creepage, clearance, and withstand voltage can be obtainedfrom most major capacitor manufacturers. These safety ratedcapacitors come in several grades depending on their intendeduse. The Y2 grade is used in line-to-ground applications wherethere is danger of electric shock and is the recommended safetycapacitor type for a stitching capacitor in a safety rated application. This type of capacitor is available in surface-mount andradial leaded disk versions. See Table 1 for a list of some Y2grade safety capacitors.Because safety capacitors are discrete components, they must beattached to the PCB with pads or through holes. This adds parasitic inductance in series with the capacitor, on top of its intrinsicinductance. It also localizes the stitching capacitor, requiringcurrents to flow to the capacitor, which can create asymmetricalimage charge paths and added noise. These discrete capacitorsare effective at frequencies up to 200 MHz. Above 200 MHz,capacitance built into the PCB layers can be very effective.Capacitance Built Into the PCBThe PCB itself can be designed to create a stitching capacitorstructure in several ways. A capacitor is formed when twoplanes in a PCB overlap. This type of capacitor has some veryuseful properties in that the inductance of the parallel platecapacitor formed is extremely low, and the capacitance isdistributed over a relatively large area.These structures must be constructed on internal layers of aPCB. The surface layers have minimum creepage and clearancerequirements; therefore, it is not practical to use surface layersfor this type of structure.Table 1. Safety CapacitorsSafetyRatingX1/Y2X1/Y2X1/Y2Working VoltageRating (VAC)250250300Isolation VoltageRating (VAC)150020002600PackageType/SizeSMT/1808Radial/5 mmRadial/7.5 mmValue (pF)150150150Rev. 0 Page 6 of 20ManufacturerJohanson DielectricsMurataVishayPart 63V7

Application NoteAN-1109Overlapping Stitching CapacitorA simple method of achieving a good stitching capacitance is toextend a reference plane from the primary and secondary sidesinto the area that is used for creepage on the PCB surface.WdW2W109713-009IAn example of a floating stitching capacitance is shown inFigure 8. The reference planes are shown in blue and green, andthe floating coupling plane is shown in yellow. The capacitanceof this structure creates two capacitive regions (shown withshading) linked by the nonoverlapping portion of the structure.To ensure that there is no dc voltage accumulated on thecoupling plane, the area on the primary and secondary shouldbe approximately equal.IThe capacitive coupling of the structure in Figure 7 is calculatedwith the following basic relationships for parallel plate capacitors:C Aεand ε ε0 εrdThe capacitive coupling of the structure in Figure 8 is calculatedwith the following basic relationships for parallel plate capacitors:lwεdCx (1)where w, d, and l are the dimensions of the overlapping portionof the primary and secondary reference planes as shown inFigure 7.The major advantage of this structure is that the capacitance iscreated in the gap beneath the isolator, where the top andbottom layers must remain clear for creepage and clearancereasons. This board area is not utilized in most designs. Thecapacitance created is also twice as efficient per unit area as thefloating plane.This architecture has only a single cemented joint and a singlelayer of FR4 between the primary and secondary referenceplanes. It is well suited to smaller boards where only basicinsulation is required.Table 2. Electrical PropertiesTypeFR4GETEKBT-EpoxyDielectric Constantat 1 MHz4.53.6 to 4.24.0dFigure 8. Floating Stitching Capacitancewhere:C is the total stitching capacitance.A is the overlap area of the stitching capacitance.ε0 is the permittivity of free space, 8.854 10 12 F/m.εr is the relative permittivity of the PCB insulation material,which is about 4.5 for FR4, as shown in Table 2.C 09713-008Figure 7. Overlapping Plane Stitching CapacitanceDielectric Strength(V/mil)1000 to 15001000 to 1200750Floating Stitching CapacitorA good option is to use a floating metal structure on an interiorlayer of the board to bridge between the primary and secondarypower planes. Note that planes dedicated to ground or powerare referred to as reference planes in this application notebecause, from an ac noise perspective, they behave the sameand can be used interchangeably for stitching capacitance.Ax εc c, ε ε0 x εr, C 1 2c1 c 2dwhere:C is the total stitching capacitance.A is the overlap area of the stitching capacitance.ε0 is the permittivity of free space, 8.854 10 12 F/m.εr is the relative permittivity of the PCB insulation material,which is about 4.5 for FR4, as shown in Table 2.C lε w 1 w 2 d w1 w 2 (2)where w1, w2, d, and l are the dimensions of the overlappingportions of the floating plane and the primary and secondaryreference planes as shown in Figure 8.If w1 w2, the equation simplifies toC lw 1ε2d(3)There are advantages and disadvantages to this structure in realapplications. The major advantage is that there are two isolationgaps, one at the primary and one at the secondary. These gapsare referred to as cemented joints, where the bonding betweenlayers of FR4 provides the isolation.There are also two sequential paths through the thickness of thePCB material. The presence of these gaps and thicknesses isadvantageous when creating a reinforced isolation barrier undersome isolation standards. The disadvantage of this type ofstructure is that the capacitance is formed under the active circuitarea so there can be via penetrations and traces that run acrossthe gaps. Equation 2 also shows that the net capacitance resulting from two capacitors in series is only half the value thatresults from using the same PCB area to form a single capacitor.Therefore, this technique is less efficient from a capacitance perunit area perspective. Overall, it is best suited to applicationsRev. 0 Page 7 of 20

AN-1109Application NoteEMI Control in the References section). Power and groundnoise reduction provides a better operating environment fornoise sensitive components near the iCoupler isolator. Bothconducted and radiated emissions are reduced proportionateto the reduction in power and ground noise. The reduction inradiated emissions is not as significant as that achieved with thestitching or edge guarding techniques; however, it significantlyimproves the power environment of the board.EDGE GUARDINGNoise on the power and ground planes that reaches the edge ofa circuit board can radiate as shown in Figure 2 and Figure 3.If the edge is treated with a shielding structure, the noise isreflected back into the interplane space (see “Minimizing EMICaused by Radially Propagating Waves Inside High SpeedDigital Logic PCBs” in the References section). This canincrease the voltage noise on the planes, but it can also reduceedge radiation.Making a solid conductive edge treatment on a PCB is possible,but the process is expensive. A less expensive solution thatworks well is to treat the edges of the board with a guard ringstructure laced together by vias. The structure is shown inFigure 9 for a typical 4-layer board. Figure 10 shows how thisstructure is implemented on the power and ground layers of theprimary side of a circuit board.GROUNDGROUND VIA EDGE FENCEAND GUARD RINGS09713-010POWERFigure 9. Via Fence Structure, Side ViewThe stack-up used for EMI test boards was signal-groundpower-signal, as shown in Figure 11. A thin core layer is usedfor the power and ground planes. These tightly coupled planesprovide the interplane capacitance layer that supplements thebypass capacitors required for proper operation of the isolator.SIGNAL/POWER09713-011SIGNAL/GROUNDFigure 11. PCB Stack-Up for Interplane CapacitanceIn addition to the ground and power planes, the capacitance canbe increased even further by filling signal layers with alternatingground and power fill. The top and bottom layers in Figure 11are labeled signal/power and signal/ground to illustrate the fillson those particular layers. These fills have the added benefit ofcreating additional shielding for EMI that leaks around the edgesof a via fence structure, keeping it in the PCB. Care should betaken when making ground and power fills. Fills should be tiedback to the full reference plane, because a floating fill can act asa patch antenna and radiate instead of shielding. Somerecommended practices for fills include Figure 10. Via Fence and Guard Ring,Shown on the Primary Power Plane e a large amount of board area is available, or wherereinforced insulation is required. There are two goals in creating edge guarding. The first goalis to reflect cylindrical emissions from vias back into theinterplane space, not allowing it to escape from the edge. Thesecond goal is to shield any edge currents flowing on internalplanes due to noise or large currents flowing on traces.Fills should be tied to their appropriate reference planealong the edges with vias, every 10 mm.Thin fingers of fill should be removed.If the fill has an irregular shape, put vias at the extremeedges of the shape.POWER FILLAVOID SMALLFILL ISLANDSThe spacing of the vias used to create the edge guard is difficultto determine without extensive modeling. Analog Devices, Inc.,test boards used 4 mm via spacing for their evaluation boards.This spacing is small enough to provide attenuation to signalsless than 18 GHzInterplane capacitance bypassing is a technique intended toreduce both the conducted and radiated emissions of the boardby improving the bypass integrity at high frequencies. This hastwo beneficial effects. First, it reduces the distance that highfrequency noise can spread in the ground and power plane pair.Second, it reduces the initial noise injected into the power andground planes by providing a bypass capacitance that is effectivebetween 300 MHz and 1 GHz (see PCB Design for Real-WorldVIA TO REFERENCEPLANEGROUNDEDVIA FENCE09713-013INTERPLANE CAPACITANCEFigure 12. Features of FillThe effectiveness of interplane capacitance is shown in Figure 13.It shows the noise generated on the VDD supply by the encoderpulses in an ADuM140x series part. In the top section, it showsRev. 0 Page 8 of 20

Application NoteAN-110960024681012141618X40304 LAYER: 4 MIL SPACING GNDTO PWR PLANEX201020050100150200250300STITCHING CAPACITANCE (pF)350400Figure 15. Peak Emissions at Frequencies of 230 MHz to 1000 MHz at 1 MbpsRate for Stitching Capacitance and Guard Options60STANDARD BOARD 5V V DDGUARD BOARD 5V V DD024681012TIME (µs)14161820Figure 13. VDD Voltage Noise for Different PCB Layouts3.3 V OPERATIONMany iCoupler products can operate with 3.3 V input andoutput supplies. Operation at lower voltages reduces generatednoise as well as production of radiated emissions. Figure 14 toFigure 17 show how emissions are reduced using a standard4-layer evaluation board with the 4-channel ADuM1402 when3.3 V supplies are used instead of 5 V supplies.STANDARD BOARD 3.3V V DD50GUARD BOARD 3.3V V DD4030201005060STANDARD BOARD 5V V DDSTANDARD BOARD 3.3V V DD50100150200250300STITCHING CAPACITANCE (pF)350400Figure 16. Peak Emissions at Frequencies of 30 MHz to 230 MHz at 10 MbpsRate for Stitching Capacitance and Guard OptionsGUARD BOARD 5V V DD60GUARD BOARD 3.3V V DDSTANDARD BOARD 5V V DDGUARD BOARD 5V V DD302010050100150200250300STITCHING CAPACITANCE (pF)350400Figure 14. Peak Emissions at Frequencies of 30 MHz to 230 MHz at 1 MbpsRate for Stitching Capacitance and Guard OptionsFigure 14 to Figure 17 also show the emissions for a variety of4-layer evaluation boards that vary in amount of primary sideto secondary side stitching capacitance and guard options.The data in these figures is used for Table 4 to Table 7 in theExample Board section to show how to apply layout techniquesto reduce emissions to meet CISPR 22 Class B emissionsstandards.Rev. 0 Page 9 of 20STANDARD BOARD 3.3V V DD50XGUARD BOARD 3.3V V DD4030X2010050100150200250300STITCHING CAPACITANCE (pF)35040009713-018PEAK EMISSIONS (dBµV/m)4009713-015PEAK EMISSIONS (dBµV/m)STANDARD BOARD 3.3V V DDGUARD BOARD 3.3V V DD09713-016PEAK EMISSIONS (dBµV/m)2 LAYER: NO GND AND PWR .944.924.90GUARD BOARD 5V V DDPEAK EMISSIONS .90STANDARD BOARD 5V V DD09713-014VDD (V)about 0.17 V p-p noise on the VDD1 pin generated on a 2-layerboard. The bottom section shows a PCB with ground and powerplanes separated by a 0.1 mm core spacing with a substantialimprovement in noise to only 0.03 V p-p. This illustrates thatif tightly spaced ground and power planes are used, the powersupply noise can be dramatically reduced.Figure 17. Peak Emissions at Frequencies of 230 MHz to 1000 MHz at10 Mbps Rate for Stitching Capacitance and Guard Options

AN-1109Application NoteCREEPAGE/CLEARANCERECOMMENDED DESIGN PRACTICESConsider the following general practices: Use a minimum stack-up of four layers.Make the GND layer as close as possible to the VDD layer tomaximize the bypass capacitance value.All vias in the power path should be as large as practical.Small vias have high inductance and generate noise. Usingmultiple small vias is not as effective in reducing via inductance as a single large via because the bulk of the currentgoes through the closest via, even if multiple paths are present.Be careful to route signal lines over a single referenceplane. It is vital to maintain the image charge path so thatimage charges do not travel by circuitous routes to meetwith the original signal on another plane.Do not route high speed lines close to the edges of the PCB.Routing data or power off boards, especially throughcables, can introduce an additional radiation concern. Feedthrough filter capacitors or similar filter structures can beused to minimize cable radiation.MEETING ISOLATION STANDARDSMost of the techniques described in this application note do notaffect board isolation, with the exception of the stitching capacitor. When stitching is implemented with a safety capacitor, thecapacitor has rated working and transient voltages, as well asspecified creepage and clearance. This makes the safety capacitor relatively easy to deal with from a certification point of view.However, its performance as an EMI suppression element islimited.The PCB stitching capacitor by its nature is most effective whenconductors are located as close to each other as possible. Formaximum performance from these elements, it is necessary topush the internal spacing requirements as far as possible, whilemaintaining safety. The limits of internal spacing depend heavilyon the standard that the system is built for. Different standardscan have completely different approaches to PCB construction.Certification agencies treat the surface layers of a multilayerPCB differently from interior layers. The surface has creepageand clearance requirements that are driven by air ionization andvoltage breakdown along dirty surfaces. Interior layers aretreated as solid insulation or permanently cemented jointsbetween solid insulation.THROUGHINSULATION09713-034 CEMENTEDJOINTFigure 18. Critical Distances in PCB designIn PCB insulation, it is important to certification agencies thatmaterials have an adequate dielectric breakdown to pass thetransient test requirements and that they are constructed in away that the insulation does not break down over time. Table 3compares four standards. Each has a different solution to whatis required to make a basic or reinforced insulation barrierinside a PCB.In the case of the IEC 60950 standard in PCBs, there is nominimum specification for distance through the insulation forfunctional or basic insulation standards. Thus, the designer hasa great deal of flexibility in board layout. Materials such as FR4must be thick enough to withstand the required overvoltage forthe life of the product.If reinforced insulatio

Control of emissions from signal cables and chassis shielding techniques are outside of the scope of this application note. EMI MITIGATION OVERVIEW . Best-practice techniques for EMI mitigation include a combination of the use of input-to-output ground plane s