Optimize Your SAR ADC DesignBonnie BakerSenior Applications [email protected] Special Thanks for InputsTim GreenRick DownsMiro OljacaThe most popular and versatile Analog-to-Digital Converter (ADC) has a SuccessiveApproximation Register (SAR) topology. These converters work by comparing ananalog voltage signal to known fractions of the full-scale input voltage and thensetting or clearing bits in the ADC’s data register. Modern SAR converters use aCapacitive Data Acquisition Converter (C-DAC) to successively compare bitcombinations. Usually these devices have an integrated sample/hold input function.It is common to use an operational amplifier (Op Amp) to directly drive the input of aSAR Analog-to-digital converter (SAR-ADC). Although this configuration is anacceptable practice in manufacturer’s data sheets, it has the potential to createcircuit performance limitations. For optimum performance, C-DAC SAR-ADCsrequire the correct front-end buffer and filter. The additional input filter or RCnetwork will relax the driving Op Amp requirements. This presentation details thereasons for an input filter and buffer amplifier to the C-DAC SAR-ADC along with ananalytical approach to selecting the filter components and op amp characteristics.1

SAR ADC System DesignOp AmpFilter-A/DSAR VDOUTSOpAmpFilterADCSignal BandwidthCharge ReservoirAcquisition TimeSlew RateCapacitor LoadIsolationData RateOutput ImpedanceNoise FilteringResolutionADC Input TopologyADC Ref InA typical input stage for a SAR ADC system is shown above. A bufferamplifier is used, driving a small RC-filter prior to the input to the ADC. We’llexamine just what these elements do for us in this seminar. Each of theseelements have a relationship to the preceding or the following element whichwill make the combination more powerful than the individuals.As we can see, for each part of this circuit, there are many considerations, allof which potentially affect the accuracy and resolution of the system. Whenchoosing components for this system, we must be mindful of all of theseconsiderations.2

The Design Tools We Will Use Data Sheet Parameters. Rules of Thumb. Tricks and Tips. Testing.Many articles have been written about choosing op amps for use in drivingADCs (see last page of this presentation). All of the articles point out thingsthat we should watch out for. From these articles and this seminar, we willobserve some guidelines and make it easier and faster to get to a gooddesign.The design procedure we will present contains some rigorous analysis, butalso observes rules of thumb, some “tricks”, and of course refers to thedatasheets of the products in our circuit. As always with analog circuitry andproof of function will be required with some testing and prototyping.3

Design ProcedureOp Amp VA/DFilter-?RFLT? VCC VREF0VCFLT?DOUT?SASignal (1)BandwidthFull-scaleRangeEOp amp (5)Input StageBandwidthOutput ROSettling TimeDCRC pair (3,4)ADC vs capCap qualityOpa vs ResistorBADC (2)Full-scale input rangeAcquisition timeKick Back Voltage &ChargeSo this is how we design our SAR-ADC circuit from beginning to end. We will firstdetermine what our input signal looks like in terms of the bandwidth and a full-scalerange. Once we understand the characteristics of our input signal, we will take alook at the ADC. The ADC that we select should match the bandwidth of our inputsignal per nyquist. This device should also have an appropriate resolution for oursignal. With the ADC selected, we will determine the acquisition time and the ADCsampling capacitance.Once we’ve selected our ADC, we determine the values of the external inputcapacitance (CFLT) and input resistance (RFLT). We will find that the quality of ourcapacitor is critical if we are concerned about the distortion that will be generated byour circuit. The value of our capacitor insurers that our ADC will have ample chargefor each conversion. The value of the resistor insurers that our operational amplifierwill be stable.We will finally select our operational amplifier. At this point, we will determine whatstyle of the input stage we need. we will also select an amplifier that has amplebandwidth for the input signal.4

1. Define Input SignalOp AmpFilter RFLTA/D VCC VREF0VCFLTDOUTVSAEDCB Highest Frequency– 1 kHz (single channel) Largest Voltage Swing– 0 to 4.096 V High Accuracy– 62.5 μV LSB size or 16-bit with range of 4.096These are characteristics of the input signal that we will use in our discussion of ourcircuit. The highest input frequency in our SAR-ADC system is 1 kHz. The largestvoltage swing of our ADC should be able to handle on its input from 0 to 4.096V.We want to have 16-bit resolution or a 62.5 μV LSB size to our analog signal. Wewill design the entire system around these specifications.5

2. Selecting the ADCOp AmpFilter RFLTA/D VCC VREF0VCFLTDOUTVSAEDCB Things we need to know––––Sampling frequency 50 kspsFull-scale input range (FSR) 4.096VHighest Resolution : 16-bitSAR Architecture : no latencyOnce we know the pertinent characteristics of the input signal we can selectthe ADC for this circuit. In particular, we want an ADC that has a minimumsampling frequency that is two times higher than the maximum signalfrequency plus an additional 10 to 20 x multiplier so that we capture a betterpicture of the input signal. With this logic we will need an ADC that has amaximum sampling frequency of at least 20 ksps.Given the sampling rate of 20 ksps, the appropriate architecture for thisapplication circuit is a SAR converter. We will use a SAR architecture for itslow latency, and chose this particular converter architecture because itoffers the highest speed and resolution combination of converters thatoperate at this sampling speed.6

ADS8320 Application Specs 16-bit, 100 kHz Micropower, Sampling AnalogTo-Digital Converter– Throughput Rate (Sampling Rate) 100 ksps tACQ (min) 1.88 μs– Input VFSR VREF 4.096 V– CSH (input sample hold capacitance) 45 pF Secondary specifications––––SNR 88 dB @ 1 kHzTHD -86 dB @ 1 kHzSINAD 84 dB @1 kHzSFDR 86 dB @1 kHzFor the TI product line, the ADS8320 best matches our input requirements.This slide shows some of the important ADS8320 specifications we’ll need toknow. Fortunately, all of these parameters are specified in the datasheet.The maximum throughput rate of the ADS8320 at 100 ksps exceeds the 20ksps requirement. The input range of the ADS8320 is equal to the referencevoltage supplied to the converter. A 4.096 reference voltage isrecommended. Specifications that we are going to need through out theremainder of this discussion is the signal acquisition time (tACQ 1.88 μs)and the value of the input capacitance of the SAR converter. In the case ofthe ADS8320, the input capacitance (CSH) is equal to 45 pF.Secondary specifications, such as Signal-to-Noise Ratio (SNR), Totalharmonic Distortion (THD), Signal-to-Noise Ratio plus Noise (SINAD), andSpurious Free Dynamic Range are specifications that we will keep our eyeon as we proceed through the design.7

A/D Converter Terms Acquisition Time (tACQ):– The time the internal A/D sample capacitor is connected to theA/D input analog signal Conversion Time (tCONV)– The time the A/D requires to convert the sampled analog inputto a digital output after the acquisition time (tACQ) is complete Throughput Rate [Sampling Rate]– Maximum frequency at which A/D conversions can berepeated– Is equal to the Acquisition time plus the Conversion time (tACQ tCONV) i.e. 100 ksps Throughput Rate [Sampling Rate] implies that aninput analog signal may be converted every 10μsBefore going further, it’s important to understand some of the timingcharacteristics of the ADC that we’ll be using.A SAR ADC takes a sample of a signal at a moment in time, and convertsthat one sample to a digital value. It takes a certain amount of time for theinput signal to be connected to the internal capacitor of the ADC and store itsvoltage on the internal sampling capacitor. The amount of time allowed toget the input voltage stored on the ADC input capacitor to the accuracyrequired by the ADC is the acquisition time of the converter.Once the sample voltage is stored on the sampling capacitor, the actualconversion process takes place, where the sample is successively comparedto known fractions of charge. The time it takes to make all of thecomparisons and generate the digital value is the conversion time.To accomplish a complete conversion, both the acquisition and conversiontimes must pass. The fastest a system can sample and convert a signalwould be the rate at which it can successively sample. The throughput rateof a converter describes the fastest speed that the ADC can successivelysample. This rate must also include the settling time of the converter’s inputstage, as well as settling times for the other amplifiers and elements in thesignal chain.8

SAR Acquisition and Conversion TimeVSData Output Register½ LSBVCSH(t)tACQVSH0t0tACQTimeVSRSWRS 0ΩSARS1CSH N-bit searchDACA typical SAR conversion cycle has two phases; a sampling phase and a conversion phase.During the sampling phase, the analog input signal charges the ADC’s Sample-and-Hold(S/H) capacitor (CSH) through the switch resistance (RSW) to a level proportional to theanalog input. The combination of the switch resistance (RSW), the source resistance (RS),and the sampling capacitor (CSH) determine the rate of change of the charge on the samplingcapacitor (CSH).The diagram in the upper left portion of this slides illustrates the rise time characteristics ofthe voltage on CSH during the acquisition phase. As expected, this rise time has a single poleresponse.Conversion begins immediately following the sampling phase with the opening of the inputswitch (S1). Conversion successively compares the unknown value of the charge stored onthe S/H capacitor to known fractions of charge. After each comparison, logic on the ADCdetermines if the unknown charge is greater or smaller than the known fractional charge.At the end of the process the data register will contain a binary value proportional to thevalue initially placed on the S/H capacitor. The user reads this value out as converted data.As shown in the diagram above, the converter we are evaluating does not have an internalinput buffer amplifier. This may not be the case with the particular SAR converter you mayuse. The product data sheet provides details on the input structure for a particular product.9

Single-pole, Time ConstantMultiplierNumber of 00030%Time Constant(k) Multiplier89111213151718The amount of time needed to settle the input structure of the SAR-ADC dependson the number of bits of the converter. This table lists the number (k) of timeconstants (τ) required to settle to within a half LSB to a given number of bits. Forour 16-bit example, we will allow the twelve time constants for the ADC input stageto settle or k 12. The time constant of the ADS8320 alone is equal to RSW ( 100 Ω)times CSH ( 45 pF, typ) or τADC CSH x RSW 4.5 ns. The input structure of theADC requires a total of k x τADC time or 540 ps to charge. When we add the externalRC network before the ADC, the time constant of the system will change to becomeτFLT which equals CFLT times RFLT.10

ADC System ModelVA/DRFLT?VSRSW50ΩtCFLT?CSHS120pF- 50pFS2 Large charge distribution must settle during tACQ Added capacitor (and possibly resistor) can reduce spike Op amp must be capable of charging Capacitance (CSH CFLT) Within acquisition time, tACQ From 0 V to (FSR - 0.5LSB)The input of a modern SAR ADC can be modeled as shown above. At any time, thesampling capacitor can have an initial voltage ranging from 0V to the supply voltage,from sample to sample. This presents a very dynamic load to the driving op amp.Because the sample capacitor may have residual charge on it from a previousconversion, it is not uncommon for this charge to discharge back out of the ADCinput terminal. This “kickback” charge injection can sometimes be seen with anoscilloscope.To help reduce this effect, and to provide a charge reservoir for charging thesampling capacitor (CSH), an RFLT CFLT circuit is added between the op amp and theADC. The op amp must be capable of driving this capacitive load, and settle fromzero volts to within full-scale range (FSR) minus 0.5LSB of VS, within the acquisitiontime of the ADC. Generally, this means that the op amp must have a low widebandopen-loop output resistance (RO). We’ll look at the op amp requirements in moredetail later.11

SAR ADC Input ChargeDistribution Op amprequirements– Must charge the ADCcap quickly &accuratelyADS8361This is a scope capture of the input of a SAR ADC, which clearly shows thecharge distribution at the input of the 16-bit ADS8361. This particularconverter (ADS8361) shows about a 20mV spike, which is equivalent to alittle more than 16LSBs.The scope photo in this slide shows the ADS8361 charge injectiontransients. This data was generated by placing a 10 kΩ resistor between thebuffer op amp and the SAR ADC input, so we could clearly see the spikes. Ingeneral, the input impedance presented to a SAR converter should never beas high as 10 kΩ. If we can see spikes like this on the input to our SAR, itmeans that the impedance of our source is too high.Even with lower impedances, we may see spikes at the input of our SARADC. The spikes are caused by the internal switching while the converter isacquiring the input signal value. If these spikes do not settle back to matchthe input value within the acquisition time of the converter, there may be ameasurement error. These spikes also present a very demanding load to thedriving op amp.The functions of the RFLT CFLT filter in front of the SAR is to provide a path forthis charge injection to come and go from, and to do some minimal isolationof the op amp output to these transients.12

ADC Conclusion Key ADC specifications per Input Signal– Sampling Rate 100 ksps– Full-scale input range 4.096 V In following discussion we will use theADS8320––––tACQ : ADC acquisition timeCSH : ADC input capacitancek : 16-bit time constant multiplierVFSR : Full-scale input range of ADCThe converter that we have chosen for our example circuit is the ADS8320. Thisconverter is capable of converting at a 100 ksps rate. The ADS8320 can alsooperate with a full-scale voltage input range of 4.096V if the reference to theconverter, VREF, is equal to 4.096V.As we define the value of the external capacitor, CFLT, we need to know theacquisition time of the converter (tACQ), the ADC input capacitance (CSH), the timeconstant multiplier for an 16-bit converter (k), and the converter full-scale inputvoltage range (VFSR).13

3. Choosing CFLTOp AmpFilter RFLTA/D VCC VREF0VCFLTDOUTVSAEDCB Provides charge to ADC sampling capacitor, CSH CFLT is the charge reservoirCFLT serves several purposes. The first purpose that this capacitor serves isto store energy to charge the ADC internal sampling capacitor (CSH).Secondly, CFLT provides a place for the internal capacitor’s charge to go.Due to the storage capabilities of CFLT, we will sometimes refer to thiscapacitor as the “flywheel” capacitor. CFLT has this alternative namebecause, like a flywheel, it stores energy for when we need it; during theacquisition time of the ADC. Another name we will use to describe CFLT ischarge reservoir.14

ADC Specs for CFLT DeterminationtACQADS8320-RFLTRSWCSH CFLTNeed to Know :: CSH, tACQ, k, VFSR tACQ 1.88 μs CSH (sampling ADC input capacitor) 45pF k 12 Worst case ΔV across CSH is VFSR– VFSR VREF 4.096 VContinuing on, the ADC values that we are going to use in our calculations are tACQ,CSH, k, and VFSR.As we select the value for CFLT, it is critical that we meet the acquisition time (tACQ)requirements of the converter. This will be specified in the manufacturer’s datasheet. The size of the external capacitor must facilitate this effort by minimizing theimpact of the charge injection on the output of the driving op amp. This charge isgenerated by the ADC input structure at the beginning of the acquisition period.We will need to know the value of the ADC input capacitance (CSH) to insure thatthe external capacitor reduces the impact of the charge injection from the converteron the operational amplifier. Again, the ADC input capacitance value can be foundin the manufacturer’s data sheet.We have identified a time constant multiplier (k, slide 10) equal to twelve for a 16-bitADC. This number will be used when we size the external capacitor.Finally, we will perform a worst case calculation using the full-scale range of theconverter as a maximum input and the initial voltage on CSH equal to zero volts.Although it is possible to characterize the charge injection characteristics of theADS8320, a worst case assumption will make our work applicable to all SARconverters.15

Capacitor Charge Transfer Prior to acquisition VIN VSHVINRSWS1CFLT-RFLTCSHRSWVINCSH ChargeReservoirVSH(a.) prior to acquisitionCFLT During acquisition– CFLT and CSH exchangecharge– VSH changes to equal VINVINCFLTRSWVSHCSH(b.) during acquisitionThis slide shows a simplified circuit for the capacitive input stage of the circuit in theprevious slide. Prior to the input signal acquisition, S1 is open (diagram a). Theinput capacitor, CFLT, has an initial voltage of VIN and the voltage across the samplecapacitor, CSH, is VSH0. S1 closes at the start of signal acquisition (diagram b). Afterthe sampling switch (S1) closes, the capacitor voltages, VIN and VCSH, start to settleto the final value of VIN as the charge quickly redistributes between CFLT and CSH.16

Ideal Value for CFLT Charge Transfer Equation: Q C x V– QSH CSH x VFSR– QSH 45pF x 4.096V 184pC IDEAL CFLT– Charge reservoir fills CSH with 1/2LSB from VS droop on CFLT 1/2LSBof VFSR VFSR / 2N :: (worst case)1/ LSB of V16 31.25 μV2FSR 4.096 V / 2– QSH QFLT QFLT CFLT x (1/2LSB from FSR)– 184pC CFLT x (31.25μV) CFLT 5.9 μFWe can calculate the charge (QSH) needed to charge the internal sampling capacitorto the input voltage. Ideally, the charge reservoir provides enough charge to theinternal sampling capacitor so that the voltage on the filter capacitor droops by lessthan 0.5LSB of VS. If we assume the worst case condition, VS equals VFSR and0.5LSB of VFSR equals 31.25 µV. This would require a filter capacitor (CFLT) of 5.9µF be placed in front of the ADC.17

IDEAL CFLT 5.9 μF: Assessment The Driving Op Amp probably– Can not directly drive a 5.9 mF capacitor– Circuit may be marginally stable– Could have transient current problems With resistor between Op Amp and capacitor– Resistor and capacitor still need to meet signalbandwidth– Resistor may not be large enough to help isolateCFLTWith a capacitance value of 5.9 μF, the op amp may not be able to drive such alarge capacitive load. If an external resistor (RFLT) is added, the RFLT CFLT timeconstant may not be small enough to allow the input signal to settle in a reasonableamount time. Moreover, the capacitor using your calculations and ADC may be toolarge and perhaps expensive.18

CFLT Suggested Modification Starting Point :: Partition the charge reservoir– 95% from CFLT– 5% from Op Amp CFLT value provides QSH with 5% droop on CFLT––––QFLT QSHQFLT CFLT x (0.05 VFSR)184pC CFLT x (0.05 x 4.096V) CFLT 898 pFWe’ll use 1000pF or 1 nF Ensure CFLT 20 x CSH– During tACQ the Op Amp must be able to replace 5% VFSR on CFLTIf we partition the charge reservoir and the op amp, the amplifier provides some ofthe current to charge the sampling capacitor. Now, as a starting point, the filter capprovides a less than 5% droop when supplying the charge. This suggests a morereasonable value for CFLT of about 898 pF – we’ll use 1 nF as a closeapproximation. Remember, all the values we find are starting points, and then we’lloptimize, so there’s no need to be too rigid about the results.As a check, we make sure that the filter capacitor value chosen is at least 20 timesthe internal capacitor value. In our case, it’s more than 20 times the size, so we’remeeting that rule of thumb.19

Capacitor Voltage Coefficient Voltage coefficient causes distortion– C C0 x (1 bVCAP)– Also has non-linear error proportional to frequencyCapacitance Change (%) Voltage and frequency coefficients impact ADC distortion20100-10-20-30-40-50-60Source: Murata0. (Vrms)2.53.0One thing to watch out for in choosing the filter capacitor is distortion. Thedistortion occurs due to the normal capacitor voltage dependantcharacteristic, meaning that the capacitance changes with the voltageapplied.An equation that describes this change in one region of the voltage curve is:C C0 ( 1 bVCAP),whereC0 is the nominal capacitance,VCAP is the voltage across the capacitance,b is the voltage coefficient of the capacitor.A plot of a typical curve of this capacitance is shown in this slide.The current or input charge travels through the ADC driving impedance,which creates a voltage drop error, which again varies with voltage. Sincethe charging current from CFLT is voltage dependant, it creates a non-linearerror. For a sine wave, this error contains harmonics.The capacitor voltage coefficient characteristic can be more pronounced insemiconductor process technologies. Since the ADC input has an internalinput RC, this distortion-producing phenomena also occurs at the input of theconverter.20

Capacitor THD N versus Frequency-60-65Y5VTHD N (dB)-70-75Z5U-80X7R-85System 50k10k200kSilver MicaThe input signal frequency across CFLT can also impact the accuracy of yourconversion. Capacitors have a voltage coefficient, which means the capacitancechanges with applied voltage. The capacitance value also tends to be nonlinear,and introduces distortion which also changes with frequency.This graph shows the characteristics of several capacitor technologies and theirTotal Harmonic Distortion plus Noise (SINAD) versus frequency performance. Thelowest line on this chart is taken using a Silver Mica capacitor. The line above theSilver Mica Capacitor data shows the system measurement. The other lines on thischart are from ceramic caps with different dielectrics - Z5U, Y5V, and X7R. Notethat these types of capacitors introduce significant non-linearity and signal distortionover frequency.Not shown on this chart is the ceramic C0G type capacitor. The C0G type capacitorclosely matches the silver mica performanceIt is critical that you select the right capacitor type for CFLT. We will find that a higherquality external capacitor (CFLT) will not degrade the AC specifications of the ADC.The larger voltage coefficient of the smaller internal ADC capacitor (CSH) will bedwarfed by the lower voltage coefficient of the larger external capacitor.21

CFLT Type and Value Requirements For our example CFLT 1 nF High quality capacitor– Low Voltage Coefficient– Low Frequency Coefficient– Capacitor Type : C0G CFLT 20 x CSH– 95% of Charge to ADC from CFLT– 5% of Charge to ADC from OPA– Dominant load of Op amp is CFLT Droop on CFLT 5%The capacitance value that we have chosen for our design example is 1 nF. Thiscapacitor should be a high quality capacitor with low voltage and frequencycoefficients. Recommended capacitor types is silver Mica or C0G.If we design the external capacitor value to be at least twenty times larger than thesize of the internal sampling capacitor, 95% of the charge required during theacquisition time comes from the external capacitor, CFLT. This minimizes the effectsof the charge redistribution on the driving amplifier. Additionally, this configurationreduces the voltage droop at the input to the SAR ADC, insuring that theinstantaneous voltage droop at the amplifier is less than 5% of the original voltagedroop without CFLT.22

4. Choosing RFLTOp AmpFilter RFLTA/D VCC VREF0VCFLTDOUTVSAEDCB Things we need to know– tACQ ADC acquisition time (1.88 μs)– k Single-pole time constant multiplier for 16-bit ADC (12)– CFLT External input capacitor to ADC (1 nF)With the capacitor chosen, we move on to the resistor, RFLT.As we work thru the resistor selection we will again need to know the acquisitiontime of the converter (tACQ), the time constant multiplier (k), and the value of the filtercapacitor (CFLT).The acquisition time of the converter will assist in choosing a resistor that balanceswith CFLT. The value of “k” will also be used in this part of the resistor valueidentification.We will use the combination of values of RFLT and CFLT to verify the stability of ourcircuit.23

First Pass Determination of RFLT Value First Pass RFLT CalculationτFLT RFLT x CFLT Filter time constant– tACQ k x τFLT 1.88 μs 12 x τFLT τFLT 157 nsThe external RFLT CFLT network must settle within the ADC acquisition time. Usingthe converter’s acquisition time (tACQ), the maximum filter time constant (τFLT forRFLT CFLT) for this circuit is 157 ns.24

RFLT Value with 40 % MarginGiven tACQ k x τFLTDesign in a margin of 40%– 60 % x tACQ k x τFLT Margin for:¾ Op Amp Output Load Transient¾ Op Amp Output Small Signal Settling Time– RFLT (0.60 x tACQ ) / ( k x CFLT) RFLT (0.60 x 1.88 ns)/(12 x 1 nF) RFLT 94.2 Ω Use RFLT 100ΩAs a rule of thumb, we will set the external RFLT CFLT settling time constant a bitfaster than ideal – 60% say, to allow a margin for error of the op amp load transientand the small signal settling time. Using this guideline, we can calculate aresistance value that is more forgiving.25

5. Choosing Op AmpOp AmpFilter RFLTA/D VCC VREF0VCFLTDOUTVSAEDCB Things we need to know– RFLT External input resistor to ADC (100 Ω)– CFLT External input capacitor to ADC (1 nF)– tACQ ADC acquisition time (1.88 μs)With our RFLT CFLT filter values chosen, we can now search for a suitable op amp todrive this system. The combination of RFLT and CFLT will be used to determine thestability of the operational amplifier. During this evaluation process, the open-loopoutput resistance of the amplifier will help to verify amplifier stability and the value ofRFLT.The acquisition time of the converter will be compared to the amplifier large signaland small signal settling time. In our evaluation we will insure that the amplifier wehave selected will settle in enough time for the ADC to complete the signalacquisition.26

Primary Op Amp Buffer SpecsSpecificationSymbolGain Bandwidth ProductGBWPClosed Loop Gain BandwidthfCLSlew Rate to Track 100kHz InputSROPAOp AmpFilter RFLTA/DCFLT0VDOUTVSAs mentioned earlier, knowing what power supplies we plan to use to power the opamp is important. It helps to narrow down the available operational amplifierchoices. In our case, we’ll opt to use a single, 5V supply.The buffer amplifier may be configured as either a follower (noninverting gain of 1V/V) or an inverting gain of –1 V/V amplifier. We’ve chosen a non-invertingconfiguration.We will pick the GBWP of the amplifier to make sure that the input signal bandwidthis accounted for, and the amplifier is stable with the RFLT CFLT load.The amplifier must have sufficient slew rate to charge the RFLT CFLT changes. Awideband amplifier will generally have a fast transient response and will be able tohandle the load transients better.27

Secondary Op Amp Buffer Specs–––––Total Harmonic Distortion (THD)Low Noise for 16-bit performanceClosed Loop Gain ErrorPeak Output CurrentInput Cross-over DistortionThe THD, noise, closed loop gain error, and peak output current capabilities aresecondary op amp specifications.At our 16-bit level, we’d like an amplifier that has extremely low distortion in oursignal range of interest. This requires digging into the op amp product data sheets,because this parameter is rarely shown in selection tables. Usually a curve isincluded in the datasheet showing THD even if it is not specified in the specificationtable.Because of our 16-bit system, a low noise amplifier is a must. The op amp datasheet has the noise specification in the Electrical Characteristics table.Another thing to consider is the open loop gain of the op amp, and how that mightcontribute to gain error. For example, an op amp with 97dB of open loop gain wouldgive us a gain accuracy to approximately a 13-bit level. Is this a problem? Probablynot – the other gain error sources in the system, from our front end to the reference,are generally much larger. Calibration at the system level can remove this error, andis generally required of any measurement system.The limit of the peak output current is calculated by using the value of the filterresistor (RFLT) we will find, and remembering that the op amp is asked to supply 5%of VFSR to recharge the flywheel capacitor.We have elected to use the operational amplifier in a buffer configuration where thegain is equal to 1 V/V. Consequently, we will use an amplifier that does not displayinput cross-over distortion.28

OP Amp Buffer Application Specs Application:–––––––Single Supply 5VBuffer – NO CM Input CrossoverSlew Rate to track 1kHz InputWideband for good gain flatness: 1kHz, G 1Wideband for fast transient response to Noise Filter TransientsLow Noise for 16 Bit performanceRRIO for 65mV to 4.935V Input and Output on 5V Supply Best Industry Choice– OPA363 or OPA364 (OPA363 with Shutdown feature)– “1.8V, 7MHz, 90dB CMRR, Single-Supply, Rail-To-Rail I/O”The absence of common-mode crossover makes the OPA363 and OPA364excellent buffer amplifiers. In addition, they have fast settling time and output drivecurrent to provide a good filter transient response. Excellent rail-to-rail performanceallows us to take full advantage of the ADS8320 dynamic signal range.29

OPA363/OPA364 Application Specs SRMIN (V/μs) 2 π f x VO

It is common to use an operational amplifier (Op Amp) to directly drive the input of a SAR Analog-to-digital converter (SAR-ADC). Although this configuration is an acceptable practice in manufacturer's data sheets, it has the potential to create circuit performance limitations. For optimum performance, C-DAC SAR-ADCs